1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method therefor and, more particularly, to a semiconductor device having a contact plug penetrating through an interlayer insulating film and to a method suitable for manufacturing the semiconductor device.
2. Description of the Background Art
FIGS. 5A and 5B are cross-sectional views for describing a series of processing operations in a former semiconductor device manufacturing method for forming a contact plug electrically connected to a silicon substrate or agate electrode. According to a former semiconductor device manufacturing method, a gate electrode 12 having a polycide structure is formed on a silicon substrate 10. The gate electrode 12 comprises a lower layer 14 of polycrystalline silicon and an upper lower 16 of metal silicide. The polycrystalline silicon layer 14 and the metal silicide layer 16 are usually formed to a thickness ranging from 500 to 1000 angstroms.
After formation of the gate electrode 12, an interlayer oxide film 18 is formed on the silicon substrate 10. Next, predetermined locations of the interlayer oxide film 18 are eliminated by means of photolithography and etching, thereby forming a contact hole 20 in the surface of the silicon substrate 10 and a contact hole 22 in the upper portion of the gate electrode 12 (see FIG. 5A).
After opening of the contact holes 20 and 22, a polycide wiring pattern 24 is formed (see FIG. 5B). The polycide wiring pattern 24 comprises a polycrystalline silicon layer 26 deposited in the contact holes 20 and 22 and on the interlayer oxide film 18, and a metal silicide 28 deposited on the polycrystalline silicon layer 26. The polycide structure mentioned above can reduce wiring resistance to a greater extent than can a single body of polycrystalline silicon. Accordingly, the former manufacturing method enables realization of a multilayer wiring structure of low resistance.
However, according to the former manufacturing method, the polycrystalline silicon layer 26 of the polycide wiring pattern 24 may sometimes be deposited on the metal silicide layer 16 which remains on the surface of the gate electrode 12. In this case, a contact layer of the metal silicide layer 16 and the polycrystalline silicon layer 26 (hereinafter referred to as a "silicide-silicon contact layer") is formed along aboundary between the gate electrode 12 and the polycide wiring pattern 24. Compared with a contact layer where polycrystalline silicon layers come into contact with each other (hereinafter referred to as a "silicon-silicon contact layer"), the silicon-silicide contact layer produces higher electrical resistance.
FIG. 6 is a cross-sectional view showing a semiconductor device manufactured under the condition that prevents a formation of the silicon-silicide contact layer. The semiconductor device shown in FIG. 6 can be manufactured by continually carrying out an etching operation for the purpose of forming the contact holes 20 and 22, until the contact hole 22 penetrates through the metal silicide layer 16. Under the foregoing condition, in the contact hole 22 there can be formed the contact layer of the polycrystalline silicon layer 14 of the gate electrode 12 and the polycrystalline silicon layer 26 of the polycide wiring pattern 24, i.e., the silicon-silicon contact layer. Consequently, under the foregoing condition, the resistance of the wiring pattern of the semiconductor device can be reduced.
However, if the etching operation is continued until the contact hole 22 penetrates through the metal silicide layer 16, there may arise a problem in which the silicon substrate 10 at the bottom of the contact hole 20 is eliminated excessively. For this reason, the method of preventing formation of the silicon-silicide contact layer by continually etching the contact hole 22 is not necessarily an ideal technique.
Under the former semiconductor device manufacturing method, the contact holes 20 and 22 are etched through use of a CF-based (fluorocarbon-based) gas, such as a C.sub.4 F.sub.8 gas, a CHF.sub.3 gas, or a CH.sub.2 F.sub.2 gas. By means of the etching step in which such an etching gas is used, fluorocarbon-based polymer is deposited to a thickness of about 50 to 100 angstroms on the surface of the silicon substrate 10 in the contact hole 20 and on the surface of the gate electrode 12 in the contact hole 22. This fluorocarbon-based polymer layer will hereinafter be referred to as an "organic layer 30." If the organic layer 30 exits in the boundary surface between the polycrystalline silicon layer 26 of the polycide wiring pattern 24 and the silicon substrate 10 or the gate electrode 12, high contact resistance will develop therebetween. Even in this respect, the former manufacturing method is apt to impart high wiring resistance to the semiconductor device.
The smaller the semiconductor device, the smaller the diameter of the contact hole. Further, the smaller the diameter of the contact hole, the more apt contact resistance is to increase further. Accordingly, reduction in contact resistance and sufficient reduction in the resistance of the wiring pattern of the semiconductor device are important measures for the pursuit of miniaturization of the semiconductor device.